Organic EL display devices are known for their thinness, high-quality image displaying capabilities and low power consumption. Organic EL display devices have a plurality of pixel circuits disposed in a matrix pattern. Each of the pixel circuits includes an organic EL element which is a self-luminous electro-optic element driven by an electric current; drive transistors; etc.
FIG. 17 is a circuit diagram which shows a configuration of a conventional pixel circuit 91. The pixel circuit 91 is disclosed in Patent Literature 1 for example. Note that hereinafter, the pixel circuit 91 shown in FIG. 17 may sometimes be called “referential prior art” for convenience. The pixel circuit 91 is disposed correspondingly to an intersection of a data line Dj (j represents a natural number) and a scanning line Si (i represents a natural number), and has one organic EL element OLED, two transistors T1, T2, and one capacitor C1. The transistor T1 is a drive transistor, whereas the transistor T2 is an input transistor. Transistors T1 and T2 are provided by n-channel thin-film transistors (Thin Film Transistor, hereinafter abbreviated as “TFT”).
The transistor T1 is in series with the organic EL element OLED, has its drain terminal connected to a power supply line which supplies a HIGH level power supply voltage ELVDD (hereinafter called “HIGH level power supply line” and will be indicated with the same reference symbol ELVDD as the HIGH level power supply voltage), and has its source terminal connected to an anode terminal of the organic EL element OLED. The transistor T2 has its gate terminal connected to the scanning line Si, and is disposed between the data line Dj and the gate terminal of the transistor T1. The capacitor C1 has its one terminal connected to the gate terminal of the transistor T1, and the other terminal connected to the source terminal of the transistor T1. The organic EL element OLED has its cathode terminal connected to a power supply line which supplied a LOW level power supply voltage ELVSS (hereinafter called “LOW level power supply line” and will be indicated with the same reference symbol ELVSS as the LOW level power supply voltage). Hereinafter, in the description of the referential prior art, a term “gate node VG” will be used for the sake of convenience to refer to a point of connection between the gate terminal of the transistor T1, the one terminal of the capacitor C1 and a conduction terminal of the transistor T2 which is located on the gate terminal side of the transistor T1.
FIG. 18 is a timing chart for describing an operation of the pixel circuit 91 in FIG. 17. Before Time Point t1, the transistor T2 is in OFF state, and the gate node VG has its electric potential maintained at an initial level (e.g., a level corresponding to writing in the previous frame period). Upon Time Point t1, the scanning line Si is selected; the transistor T2 is turned ON; and a data voltage which represents a brightness of a pixel (sub-pixel) formed by the pixel circuit 91 in the i-th row (hereinafter called “data voltage in the i-th row” and will be indicated with a reference symbol Vdatai) is supplied to the gate node VG via the data line Dj and the transistor T2. Thereafter, for a period until Time Point t2 is reached, the electric potential at the gate node VG varies following the data voltage Vdatai. In this process, the capacitor C1 is charged with a differential potential between the potential at the gate node VG and a source potential of the transistor T1, i.e. to the gate-source voltage Vgs. When Time Point t2 is reached, the transistor T2 is turned OFF, finalizing the value of the gate-source voltage Vgs held by the capacitor C1. The transistor T1 supplies a drive current to the organic EL element OLED in accordance with the gate-source voltage Vgs held by the capacitor C1. As a result, the organic EL element OLED emits light at a brightness determined by the drive current. In addition to the above, Patent Literature 2, 3 disclose other pixel circuits and organic EL display devices relevant to the present invention.